1. Field of the Invention
The invention relates generally to the field of electronic data processing systems, and more specifically to the portions thereof for storing data. The invention finds particular utility in register arrays used, for example, in processors and in other data storage elements, particularly those fabricated in integrated circuit chips.
2. Description of the Prior Art
Microprocessors generally include a plurality of storage elements that are arrayed in registers, each register having a selected number of the storage elements. The registers store information in a register-by-register basis, the information being used by processing elements in the microprocessor. Each register in the array is individually-addressable, and when a register is addressed, the contents of all of the storage elements forming the register, representing the states or conditions of the storage elements, are transmitted to the other circuitry on the microprocessor.
Each storage element in a register array typically includes a flip-flop having two stable states, each representing a binary one or zero, an input circuit and one or more output circuits. If a register array is used as a general purpose register for storing addressing, control or arithmetic information, for example, it may be connected to the inputs of an arithmetic/logic unit (ALU). Typical ALUs normally have two input terminals for receiving input signals from two input buses, each bus including bit or signal lines connected to corresponding storage elements in all of the registers. Registers selected by register addressing circuitry transmit signals representative of the states of the respective flip-flops over the bit lines of the input buses to the inputs of the ALU. The storage elements also may be provided with two output terminals, each of which is connected to transmit signals representing the stored contents over one of the output buses to the corresponding input terminals of the ALU. The register output terminals are individually-selectable or addressable on a register-by-register basis, so that each of the ALU input terminals may contemporaneously receive signals from different ones of the registers.
In present register arrays, the signal lines provide for differential signals to the flip-flops forming the storage elements. Such differential signals typically allow for a reduction in noise interference with the input signal, but also requires two input lines each carrying one of the differential signals. In addition, since the registers are also separately addressable, the register inputs require input transistors on each of the differential lines. Both the second lines and the input transistors therefor take up valuable chip space on a microprocessor, reducing the amount of space available for other circuitry and making layout thereof more difficult. Accordingly, it is desirable to eliminate the differential arrangement and have a single line, or rail, for the storage elements in the registers.
Between the outputs of the storage elements and any downstream circuitry, for example, the inputs of an ALU or terminals for connection to a bus, is a set of sense amplifiers which amplify the output signals from the addressed storage elements. The output signals from the flip-flops may be relatively weak, since the transistors forming the flip-flops may be required to drive bit lines which have a relatively high capacitance. Furthermore, in view of the high capacitance of the signal lines, the time required for the signals on the bit lines to achieve the levels required to be sensed by the sense amplifiers may be quite long. The sense amplifiers must be able to rapidly detect the weak signals from the register storage elements and determine the level of the signals. Accordingly, it is desirable to provide a sensitive sense amplifier to reduce the amount of delay of the sense amplifier sensing the state of the signal from the selected flip-flop.